ABSTRACT
A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.
> provides up-to 50% area reduction and reduced power consumption by a factor ten
I think its a miracle.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
eDRAM isn't the same as 1T-SRAM, which isn't quite the same as 1T-1C SRAM...
But overall they run into the same problems that you mention; it's just too hard to get a capacitor in play.
There is Zeno Semi's Bi-SRAM, buuuut it hasn't seemed to catch on for one reason or another.
Not sure what this source is, but it looks sketchy.
I tried to make some estimations: modern CPUs can work at 4 GHz, which is 250 ps/cycle. Modern CPUs allegedly can do 64-bit addition in that one clock cycle. Carry-lookahead adder requires a fat 63-input AND followed by fat 63-input OR for computing the carry for MSB, which can be implemented as 2×8 layers of 2-input gates or 2×3 layers of 4-input gates, or 2×2 layers of 8-input gates. Then you add the carry to the sum which requires a XOR which is probably like 2 layers of standard gates. Then you need to respect set-up time for the flip-flop, and account for a propagation inside it. A flip-flop (2 latches) is at least 2 layers of gates. So if we consider 4-input gates, the path would be 6 + 2 + 2 = 10 layers, and the propagation time for one gate should be 250÷10 ~ 25 ps.
Is that correct or not? Or the clock of CPU is limited by thermal limits and not by propagation time? Or there are some tricks that allow using slower transistors?
Please help me solve this puzzle.